The present invention relates to the field of programmable logic and devices therefor. More specifically, in one embodiment the invention provides an improved programmable logic device with enhanced cascade function as well as associated methods of operation.
Programmable logic devices (PLDs) are well known to those in the electronics art. Such programmable logic devices are commonly referred to as PALs (Programmable Array Logic), PLAs (Programmable Logic Arrays), FPLAs (Field Programmable Logic Arrays), EPLDs (Electronically Programmable Logic Devices), EEPLDs, LCAs (Logic Cell Arrays), FPGAs (Field Programmable Gate Arrays), and the like. Such devices are used in a wide array of applications where it is desirable to configure or program an off the shelf device for a specific application. Such devices include, for example, the well known Classic.TM. EPLDs, MAX.RTM. 5000 EPLDs, and FLEX.RTM. EPLDs all made by Altera.RTM..
These devices, while similar in some aspects of overall functionality, may be of very different types in terms of circuit architecture. One family of PLDs uses a sum-of-products (SOP) architecture whereby each output is the ORed sum of a number of ANDed product terms of the inputs. This family is represented by the Altera MAX.RTM. and Classic.TM. 5000 EPLDs. Another family of PLDs uses look-up tables (LUTS) to perform logic functions. This family is represented by the Altera FLEX.RTM. EPLDs.
Modern PLDs generally are constructed from small functional units variously referred to as logic modules or macrocells and herein referred to as logic elements (LEs). These LEs are typically identical or nearly identical throughout the PLD and perform a function that is a sub unit of the function of the entire PLD. For example, in a PLD based on a LUT architecture, the LEs might each be four input/one output LUTs. PLDs generally include an interconnect structure of conductors to provide a mechanism for selectably connecting the inputs and outputs of the LEs in order to perform the PLD functionality.
Larger PLD's of both the SOP and LUT type generally group the smaller LEs into larger functional units herein referred to as logic array blocks (LABs). The LABs can contain within them a local LAB interconnect that allows signals in one LE to be selectively connected to signals in a different LE in the same LAB. In such an architecture, a distinction is made between this LAB-interconnect (or local interconnect) and the interconnect structure between LABs that is referred to as the global interconnect (or general interconnect). The LAB-interconnect transmits signals from the global interconnect to the inputs of the individual LEs through a number of LAB-input lines. The LABs may be connected to one another and to input and output circuits by means of the global interconnect.
While such devices have met with substantial success, such devices also meet with certain limitations.
Some prior art programmable logic devices (PLD) enhanced their functionality by providing "cascade" circuitry whereby the output of a logic element could be logically ANDed with the output of an adjacent logic cell. Such an arrangement allowed, for example, the output of a single logic element to be not only a function of its four inputs but to be any function of its four inputs ANDed with any function of the four inputs of its adjacent LE. While this circuitry allowed some additional functionality, its usefulness was limited. Because the cascade circuitry allowed combining of outputs only, only functions of more than four variables that have a function of up to four variables ANDed with another function of up to four variables can be implemented.
From the above it is seen that an improved programmable logic device is desired.